Electrically erasable and programmable read-only memories (EEPROMs), in particular, “flash” type EEPROMs (hereinafter flash memories), have become an essential requirement for many portable electronic devices such as “smart” phones, tablet computing devices, and cameras, as but a few examples. Flash memories include both NAND and NOR types. NAND flash memories have higher densities than NOR flash memories, and thus may be less costly per bit. However, unlike NAND flash memories, NOR flash memories can be programmed on a byte-by-byte basis. Accordingly, NOR type flash memories are typically used for storing data, such as code, that is more frequently programmed on a byte-by-byte basis, while NAND type flash memories may be used to store large data files.
Most memory devices, including NAND and NOR type flash memories and dynamic random access memory (DRAM), are organized as an array of memory cells. FIG. 1 depicts such an array 1000, which includes memory cells 1001-1016 organized as an array. A source line 1024 is connected to every memory cell 1001-1016. A word line 1020 is connected to memory cells 1001-1004. Another word line 1021 is connected to memory cells 1005-1008. A word line 1022 is connected to memory cells 1009-1012. A word line 1023 is connected to memory cells 1013-1016. A bit line 1030 is connected to memory cells 1001, 1005, 1009 and 1013. A bit line 1031 is connected to memory cells 1002, 1006, 1010 and 1014. A bit line 1032 is connected to memory cells 1003, 1007, 1011 and 1015. A bit line 1033 connected to memory cells 1004, 1008, 1012 and 1016. Each memory cell is built in a substrate 1019 (shown in FIG. 2).
The memory cells (1001-1016) at the array points (intersections of word lines WL0-WL3 and bit lines BL0-BL3) store one or more bits of data and are addressable by addresses that include row addresses and column addresses. Each row can correspond to a word line, WL0-WL3. When a given word line (i.e., a row) is selected, each column 1030-1033 represents a bit line, BL0-BL3, in the word line corresponding to the selected word. The value of the charge held in the corresponding memory cell for a given word line and bit line is the value associated with the word/bit address of that memory cell. For example, the charge value inside memory cell 1001 is associated with the word corresponding to WL0 and the bit corresponding to BL0. Accordingly, the value of the memory cell 1001 is retrieved from the array 1000 by activating the word line WL0, at row 1020, and the bit line BL0 at column 1030, and then measuring the current that results when the cell 1001 is thus connected to the bit line BL0 at column 1030. The common source line 1024 is connected to each memory cell 1001-1016, and is maintained at a generally fixed voltage level (potentially including, ground level).
In memory arrays made up of NOR flash memories, memory cells such as the memories 1001 through 1016 of FIG. 1 are each typically implemented at a given array point as a horizontally oriented transistor, an example of which is shown in FIG. 2. Each transistor acts as a memory cell (hereinafter, “cell”).
FIG. 2 illustrates a conventional transistor 1006 memory cell from FIG. 1. Transistor 1006 includes a source 1051 connected to a common source line (e.g., 1024 of FIG. 1), a drain 1052 connected to bit line 1031 (BL1) and a control gate 1050 connected to a word line (e.g., 1021 WL1 in FIG. 1). The transistor 1006 also includes a floating gate 1060, which serves as a charge storage medium, an oxide layer 1070 between the control gate 1050 and the floating gate 1060, and an oxide layer between the floating gate 1060 and part of the substrate 1019. The floating gate 1060 is insulated by the oxide layer 1070 between the control gate 1050 and the floating gate 1060. The value stored by the memory cell 1006 is held as a charge 1061 inside the floating gate 1060, and is retrieved by activating the word line corresponding to control gate 1050 and activating BL1 1031, and then measuring the value of the current that flows between source 1051 through a source line (e.g., 1024) and bit line BL1 1031. The value of the current is a function of the charge 1061. As is known to those skilled in the art, the floating gate 1060 can hold charge at more than one location. For example, in some nitride storage-based technologies, charge may be stored in two locations, and hence one transistor may store two data bits.
It is desirable to achieve higher densities in flash memory devices. To address this need, some flash memory array architectures have been proposed in which the flash memory cells are vertically oriented within the substrate. Such architectures achieve higher densities than the sort of architectures shown in FIG. 2, in which the flash memory cells are horizontally oriented within the substrate.
FIG. 3 illustrates a conventional pair of memory cells 1101 built in to a substrate 1100 that would lie at each array point of a vertically oriented flash memory array. The cell-pair 1101 includes a vertically oriented trench 1110 etched into the substrate 1100. The cell-pair 1101 further includes two sources 1120, 1130 at the bottom of and on either side of the trench 1110, two drains 1140, 1150 at the top of and on either side of the trench 1110, two control gates 1121, 1131, and two floating gates 1141, 1151. The source-drain-control-gate-floating gate combination 1120, 1140, 1121, 1141 forms a first flash cell 1125 extending down the left-hand wall of the trench 1110, while the source-drain-control-gate-floating gate combination 1130, 1150, 1131, 1151 forms a second flash cell 1135 extending down the right-hand wall of the trench 1110. Each floating gate, 1141, 1151, holds a charge 1143, 1153 respectively, that represents the value stored by memory cell 1125, 1135 respectively. Each floating gate 1141, 1151 can hold more than one charge if, for example, nitride-based storage media technology is used. Each array point of a vertically oriented flash array thus has two cells 1125, 1135, which each can hold one or more charges, as compared to the single cell that lies at each array point of a horizontally oriented flash array (as shown in FIG. 1), thus resulting in a two-fold increase in the density of a flash array.
An example of a vertically oriented flash memory array architecture is proposed in U.S. Pat. No. 7,230,848 (hereinafter the '848 patent). With the vertically oriented array of FIG. 3, the width of each trench is roughly half as wide as the pitch of the fabrication technology being used to build the memory arrays (i.e., if the pitch is 90 nm, the width of the trench will be 45 nm in order to achieve economical densities). To build such an array, two word lines are placed side by side in a narrow trench. In such an array, electromagnetic interference phenomena such as charge leakages, over-charging, and capacitance-coupling (hereinafter, referred to as disturbs) between its more closely spaced neighboring memory cells may occur. More specifically, using present fabrication technology, the width of the trench separating each cell of a cell pair, and thus the distance between the two cells of a cell pair, is typically 45-65 nm, while the distance between neighboring cell pairs is also typically 45-65 nm. At these geometries, as each cell on either side of a cell-pair is activated, disturbs between the cells across each trench (“intra-cell-pair disturb”) become more likely. Applying increased densities may also result in disturbs between cells that belong to different neighboring cell-pairs (“inter-cell-pair disturb”). As each such neighboring cell is activated, disturbs between the cells across the substrate and one more trenches become more likely.
Dynamic random access memories (DRAMs) enjoy wide application in various devices. DRAMs may store data as a charge with a capacitance, and enjoy relatively low power consumption at the cost of being volatile, and requiring periodic refresh (i.e., recharging of a capacitor). Some conventional DRAMs may have storage capacitors formed in a substrate or over a substrate.